The task of this IC is to amplify signals picked up by chamber wires, compare them against an external threshold and transmit the results to the acquisition electronics. The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption.

As the basic requirement for the frontend is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity for sensitivity and threshold setting is needed; cost and space reasons force us to attain this goal without any equalization at wafer or board level so special care was taken at design phase to minimize offsets and mismatches.

One integrated circuit contains 4 complete analog chains, each made of a charge preamplifier and a simple shaper with baseline restorer, whose output is compared with an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels.

A fast enable/disable output feature is implemented, separately, for right and left channels; also, each channel can be singularly disabled at shaper level (return to normal operation can take almost 10us).

Included in the ASIC are a bias voltage source common to all channels and a temperature sensor for slow control purposes.